1. Field of the Invention
The present invention relates to a positional offset measurement pattern unit for measuring a positional offset between a plurality of via-plugs and a plurality of interconnections formed in an insulating interlayer of a multi-layered wiring structure, a semiconductor device featuring such a positional offset measurement pattern unit and a positional offset measurement method which is carried out by using such a positional offset measurement pattern unit.
2. Description of the Related Art
In a process of manufacture of semiconductor devices, various electronic elements, such as transistors, resistors, capacitors and so on, are produced in a semiconductor substrate, and then a multi-layered wiring structure is constructed on the semiconductor substrate.
For example, the construction of the multi-layered wiring structure can be carried out by using a dual-damascene process. In this case, the multi-layered wiring structure includes a plurality of insulating interlayers stacked in order, and each of the insulating interlayer has a plurality of via-plugs and a plurality of interconnections formed therein, with each of the via-plugs being suitably connected to any one of the interconnections.
In particular, in the dual-damascene process, in order to form the via-plugs, a plurality of via-holes are formed in the insulating interlayer by an anisotropic etching process or dry etching process using a photoresist pattern layer having a plurality of openings corresponding to the via-holes. Then, in order to form the interconnections) a plurality of trenches are formed in the insulating interlayer by an anisotropic etching process or dry etching process using a photoresist pattern layer having a plurality of openings corresponding to the trenches. Subsequently, the via-holes and the trenches are stuffed with a suitable metal material by an electroplating process, resulting in the formation of the via-plugs and the interconnections. Namely, the via-plugs are formed by stuffing the via-holes with the metal material, and the interconnections are formed by stuffing the trenches with the metal material.
The photoresist pattern layer for forming the via-holes is formed on the insulating interlayer by a photolithography process using a photomask. After the formation of the via-holes is completed, the photoresist pattern is removed from the insulating interlayer. Then, the photoresist pattern layer for forming the trenches is formed on the insulating interlayer by a photolithography process using a photomask.
Note, in the above-mentioned dual-damascene process, although the formation of the via-holes is carried out prior to the formation of the trenches, the formation of the trenches may be carried out prior to the formation of the via-holes.
In either event, before the via-plugs and the interconnections can be properly arranged with respect to each other, the photomask used to form the via-holes and the photomask used to form the trenches have to be individually and correctly positioned with respect to the semiconductor substrate. Nevertheless, one or two of the photomasks may be erroneously positioned with respect to the semiconductor substrate, so that the arrangement of the via-plugs and the arrangement of the interconnections may be relatively offset from each other.
When the arrangement of the via-plugs and the arrangement of the interconnections may be relatively offset from each other, a part of the via-plugs may become abnormally close to a part of the interconnections. When a distance between a via-plug and an interconnection is too small, a breakdown may occur between the via-plug and the interconnection, resulting in leakage of current therebetween.
Accordingly, during the construction of the multi-layered wiring structure, whenever a plurality of via-plugs and a plurality of interconnections are formed in an insulating interlayer, it is desirable to determine whether the via-plugs and the interconnections are correctly arranged with respect to each other, if necessary.
Japanese Laid-Open Patent Publication (KOKAI) No. H10-050703 discloses a prior art positional offset measurement pattern unit including plural sets of metrical via-plugs and metrical interconnections which are simultaneously formed in an insulating interlayer when a plurality of proper via-plugs and a plurality of proper interconnections are formed in the insulating interlayer, for the purpose of measuring a positional offset between the arrangement of the proper via-plugs and the arrangement of the proper interconnections.
In particular, the metrical interconnections are arranged along one direction in parallel to each other at a regular intervals, and the metrical via-plugs are combined with the respective metrical interconnections so that respective distances between opposite ends of the metrical via-plugs and the metrical interconnections gradually and regularly vary along the aforesaid one direction.
When the proper via-plugs are properly arranged with respect to the proper interconnections, the respective distances between the ends of the metrical via-plugs and the metrical interconnections are gradually and regularly decreased from a first outermost set of a metrical via-plug and a metrical interconnection toward a give middle set of a metrical via-plug and a metrical interconnection, with each of the distances being defined as a positive distance. Further, the respective distances between the ends of the metrical via-plugs and metrical interconnections are gradually and regularly decreased from the middle set of the metrical via-plug and the metrical interconnection toward a second outermost set of a metrical via-plug and a metrical interconnection, with each of the distances being defined as a negative distance so that the metrical via-plugs are electrically connected to the respective metrical interconnections.
In short, when the proper via-plugs are correctly arranged with respect to the proper interconnections, the metrical via-plugs are electrically isolated from the respective metrical interconnections in the range from the first outermost set of a metrical via-plug and a metrical interconnection to the middle set of a metrical via-plug and a metrical interconnection, and the metrical via-plugs are electrically connected to the respective metrical interconnections in the range from the middle set of the metrical via-plug and the metrical interconnection to the second outermost set of the metrical via-plug and the metrical interconnection.
On the other hand, when the proper via-plugs are offset from the proper interconnections in the direction perpendicular to the aforesaid direction along which the metrical interconnections are arranged in parallel to each other, either the number of the sets of metrical via-plugs and metrical interconnections electrically connected to each other or the number of the sets of metrical via-plugs and metrical interconnections electrically isolated from each other varies.
Namely, when the proper via-plugs and the proper interconnections are offset from each other so that the metrical via-plugs are shifted toward the metrical interconnections, i.e., so that the metrical via-plugs are positively shifted with respect to the metrical interconnections, the number of the sets of metrical via-plugs and metrical interconnections electrically connected to each other is increased, and the number of the sets of metrical via-plugs and metrical interconnections electrically isolated from each other is correspondingly decreased.
On the contrary, when the proper via-plugs and the proper interconnections are offset from each other so that the metrical via-plugs are apart from the metrical interconnections, i.e., so that the metrical via-plugs are negatively shifted with respect to the metrical interconnections, the number of the sets of metrical via-plugs and metrical interconnections connected to each other is decreased, and the number of the sets of metrical via-plugs and metrical interconnections electrically isolated from each other is correspondingly increased.
Thus, in Japanese Laid-Open Patent Publication (KOKAI) No. H10-050703, by counting either the number of the sets of metrical via-plugs and metrical interconnections electrically isolated from each other or the number of the sets of metrical via-plugs and metrical interconnections electrically connected to each other, it is possible to measure a positional offset between the arrangement of the proper via-plugs and the arrangement of the proper interconnections.
It has now been discovered that the above-mentioned prior art positional offset measurement pattern unit has problems to be solved as mentioned below.
With the recent advance of miniaturization and integration of semiconductor devices, proper via-plugs and proper interconnections to be formed in an insulating interlayer have become increasingly smaller, and thus it is necessary to more precisely and accurately measure a positional offset between the arrangement of the proper via-plugs and the arrangement of the proper interconnections. Nevertheless, the prior art positional offset measurement pattern unit does not achieve a precise and accurate measurement between the proper via-plugs and the proper interconnections, because the number of the sets of metrical via-plugs and metrical interconnections has to be enormously increased before the precise and accurate measurement can be carried out. However, the increase of the number of the sets of metrical via-plugs and metrical interconnections must be suppressed, or else a space for incorporating the positional offset measurement pattern unit in the insulating interlayer becomes much larger.